1. Field of the Invention
The present invention generally relates to printed circuit boards, methods of fabricating the printed circuit boards, and semiconductor devices, and more particularly to a printed circuit board having a capacitor that is electrically coupled to a semiconductor chip, a method of fabricating such a printed circuit board, and a semiconductor device having such a printed circuit board.
2. Description of the Related Art
FIG. 1 is a cross sectional view showing an example of a conventional semiconductor device which reduces an inductance between a semiconductor chip and an internal capacitor of a printed circuit board, by electrically connecting the semiconductor chip and the capacitor by a minimum distance.
A semiconductor device 200 shown in FIG. 1 includes a printed circuit board 201, a semiconductor chip 202, and external connection terminals 203. The printed circuit board 201 has insulator layers 211 and 225, pads 212, a capacitor 213 having a pair of electrodes, vias 218, 219, 226 and 227, wirings 222 and 223, connection pads 231 and 232 for external connection, and a solder resist layer 234.
The capacitor 213 is embedded in the insulator layer 211. Each pad 212 has a bonding surface 212A for flip-chip bonding of the semiconductor chip 202 which will be described later. The pads 212 are embedded in the insulator layer 211 so that the bonding surfaces 212A approximately match a surface 211A of the insulator layer 211.
The capacitor 213 is disposed immediately under the pads 212. One of the pair of electrodes of the capacitor 213 is electrically connected to the pads 212 at portions located on an opposite end from the bonding surfaces 212a, via (that is, by way of) internal connection terminals 215. The capacitor 213 functions as a decoupling capacitor for reducing power supply noise caused by changes in current consumption of the semiconductor chip 202. Pads 216 which electrically connect to the other of the pair of electrodes of the capacitor 213 are provided on the surface of the capacitor 213 located on an opposite end from the surface provided with the internal connection terminals 215.
The vias 218 are embedded in the insulator layer 211, and electrically connect the pads 212 to the wirings 222. The vias 219 are embedded in the insulator layer 211, and electrically connect the pads 216 to the wirings 223.
The wirings 222 are provided on a surface 211B of the insulator layer 211, located on an opposite end from the surface 211A of the insulator layer 211. The wirings 222 are formed integrally with the vias 218. The wirings 222 are electrically connected to the pads 212 via the vias 218.
The wirings 223 are provided on the surface 211B of the insulator layer 211. The wirings 223 are formed integrally with the vias 219. The wirings 223 are electrically connected to the pads 216 via the vias 219.
The insulator layer 225 is provided on the surface 211B of the insulator layer 211 so as to expose portions of the wirings 222 and 223. The vias 226 are embedded in the insulator layer 225, and the vias 226 are electrically connected to the wirings 222. The vias 227 are embedded in the insulator layer 225, and the vias 227 are electrically connected to the wirings 223.
The connection pads 231 are provided on a surface 225A of the insulator layer 255, located on an opposite end of a surface of the insulator layer 225 making contact with the insulator layer 211. The connection pads 231 are formed integrally with the vias 226. The pads 231 are electrically connected to the wirings 222 via the vias 226.
The connection pads 232 are provided on the surface 225A of the insulator layer 225. The connection pads 232 are formed integrally with the vias 227. The connection pads 232 are electrically connected to the wirings 223 via the vias 227.
The solder resist layer 234 is provided on the surface 225A of the insulator layer 225. The solder resist layer 234 includes openings 234A that expose the connection pads 231, and openings 234B that expose the connection pads 232.
The semiconductor chip 202 is flip-chip bonded on the bonding surfaces 212A of the pads 212. Hence, terminals of the semiconductor chip 202 are electrically connected to the capacitor 213 via the pads 212 and the internal connection terminals 215. For example, a semiconductor chip which operates at high frequencies may be used for the semiconductor chip 202.
The external connection terminals 203 are provided on portions of the connection pads 231 that are exposed via the openings 234A, and on portions of the connection pads 232 that are exposed via the openings 234B. For example, a Japanese Laid-Open Patent Publication No. 2003-197809 proposes a structure having exposed connection terminals.
However, the operating frequency of the semiconductor chip 202 has increased in recent years, and an inductance component generated from the capacitor 213 introduces undesirable effects on the semiconductor chip 202, such as an erroneous operation of the semiconductor chip 202.
On the other hand, if the semiconductor chip 202 has various frequency characteristics, the single capacitor 213 within the printed circuit board 201 cannot cope with the various frequency characteristics of the semiconductor chip 202.